The present invention relates to a data transfer circuit for transferring data between a data processor and a peripheral device, and more particularly relates to a data transfer circuit having a random access memory device for storing data being repetitively read or written by a data processor and a data processing system.
U.S. Pat. No. 4,342,095 to Goodman for "Computer Terminal", issued July 27, 1982, discloses a computer system terminal wherein data may be fetched from a random access memory (RAM) by addressing the RAM using a program counter within the central processing unit of the computer system. Data is thus fetched from the RAM without the use of a direct memory access circuit.
U.S. Pat. No. 4,258,430 to Tyburski for "Information Collection and Storage System with Removable Memory", issued Mar. 24, 1981, discloses a removable memory pack for storing digital data having a RAM and an address counter which is reset to zero and incremented by timer pulses to access the memory locations in the RAM.
U.S. Pat. No. 4,467,420 to Murakami et al. for "One-Chip Microcomputer", issued Aug. 21, 1984, discloses a microcomputer which includes a central processing unit, a direct memory access controller and a random access memory. In one embodiment shown in FIG. 3, an address counter is controlled by the direct memory access controller for sequentially reading out a plurality of data words from the random access memory.
In U.S. Pat. No. 4,598,362 to Kinjo et al. for "Buffer Apparatus for Controlling Access Requests Among Plural Memories and Plural Accessing Devices", issued July 1, 1986, discloses request buffer apparatus for the transfer of data from a plurality of memory banks to a direct memory access unit. The request buffer apparatus includes buffer read address generators which are loaded with the starting address from the request buffers, and whose address count is incremented by one in response to each write request signal, and is decremented by one in response to each read request signal.
U.S. Pat. No. 4,599,689 to Berman for "Continuous Data Transfer System", issued July 8, 1986, discloses an apparatus which controls sequential direct memory access transfers between a plurality of buffer memories and a data translation device. A processor places an address in the apparatus the block of data resides. The apparatus logic generates addresses for sequentially transferring data words from the main memory.